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ST
Sitronix
1. INTRODUCTION
ST7576
66 x 102 Dot Matrix LCD Controller/Driver
The ST7576 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 102 segments and 65 common with 1 ICON driver circuits. This chip is connected directly to a microprocessor, accepts 3-line or 4-line serial peripheral interface (SPI), I2C interface or 8-bit parallel interface, display data can stores in an on-chip display data RAM of 66 x 102 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Single-chip LCD controller & driver Driver Output Circuits 102 segment / 65 common+1 ICON common (1/66 duty) 102 segment / 16 common+1 ICON common (1/17 duty) (1/17 duty is under partial screen mode) On-chip Display Data Ram Capacity: 66X102=6,732 bits Generation of intermediate LCD bias voltages Oscillator requires no external components (external clock also possible) Voltage converter X4; X5 Voltage follower On-chip electronic contrast control function (255 steps) External RESB (reset) pin Logic supply voltage range VDD1 -VSS : 1.8 to 3.3V VDD2 -VSS : 2.4 to 3.3V
Microprocessor Interface 8-bit parallel bi-directional interface with 6800-series or 8080-series 4-line SPI (serial peripheral interface) available (only write operation) 3-line SPI (serial peripheral interface) available I C (Inter-Integrated Circuit) Interface
2
Display supply voltage range (V0) Application Vop range: 4V-9.5V Programmable Max V0: 10.5V
On-chip Low Power Analog Circuit Generation of LCD supply voltage
Temperature range: -30 to +85 degree
ST7576
6800 , 8080 , 4-Line , 3-Line interface (without I2C interface) I2C interface
ST7576i
Ver 1.0
1/54
2007/01/29
ST7576
3. ST7576 Pad Arrangement
Chip Size: 5570 um x770 um Bump Height: 15 um Chip Thickness: 480 um Bump Pitch: (minimum) PAD Number 1~27, 130~156, 157~163, 243~250: 28~129: 27~28 129~130 163~164 164~207, 208~211,222~228,229~235,236~242 207~208 211~212 Pitch 37.20 33.00 62.90 60.69 329.57 59.30 131.83 71.30 PAD Number 212~213 213~216,218~221 216~217,217~218 221~222 228~229 235~236 242~243 Unit: um Pitch 46.65 33.30 38.80 46.30 66.40 62.45 79.90
* Refer to "Pad Center Coordinates" section for ITO layout.
Fig 1
Ver 1.0 2/54 2007/01/29
ST7576
Pad Center Coordinates 66 Duty (TMY=0)
PAD NO. PIN Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
X 2695.50 2658.30 2621.10 2583.90 2546.70 2509.50 2472.30 2435.10 2397.90 2360.70 2323.50 2286.30 2249.10 2211.90 2174.70 2137.50 2100.30 2063.10 2025.90 1988.70 1951.50 1914.30 1877.10 1839.90 1802.70 1765.50 1728.30 1665.39 1632.39 1599.39
Y 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 282.75 282.75 282.75
COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] COM[44] COM[43] COM[42] COM[41] COM[40] COM[39] COM[38] COM[37] COM[36] COM[35] COM[34] COM[33] SEG[0] SEG[1] SEG[2]
Fig 2
Ver 1.0 3/54
30
2007/01/29
ST7576
PAD NO.
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
PIN Name SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32]
X 1566.39 1533.39 1500.39 1467.39 1434.39 1401.39 1368.39 1335.39 1302.39 1269.39 1236.39 1203.39 1170.39 1137.39 1104.39 1071.39 1038.39 1005.39 972.39 939.39 906.39 873.39 840.39 807.39 774.39 741.39 708.39 675.39 642.39 609.39
Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75
PAD NO. PIN Name
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
X 576.39 543.39 510.39 477.39 444.39 411.39 378.39 345.39 312.39 279.39 246.39 213.39 180.39 147.39 114.39 81.39 48.39 15.39 -17.60 -50.60 -83.60 -116.60 -149.60 -182.60 -215.60 -248.60 -281.60 -314.60 -347.60 -380.60
Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75
SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62]
Ver 1.0
4/54
2007/01/29
ST7576
PAD NO. PIN Name
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
X -413.60 -446.60 -479.60 -512.60 -545.60 -578.60 -611.60 -644.60 -677.60 -710.60 -743.60 -776.60 -809.60 -842.60 -875.60 -908.60 -941.60 -974.60 -1007.60 -1040.60 -1073.60 -1106.60 -1139.60 -1172.60 -1205.60 -1238.60 -1271.60 -1304.60 -1337.60 -1370.60
Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75
PAD NO. PIN Name
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
X -1403.60 -1436.60 -1469.60 -1502.60 -1535.60 -1568.60 -1601.60 -1634.60 -1667.60 -1728.30 -1765.50 -1802.70 -1839.90 -1877.10 -1914.30 -1951.50 -1988.70 -2025.90 -2063.10 -2100.30 -2137.50 -2174.70 -2211.90 -2249.10 -2286.30 -2323.50 -2360.70 -2397.90 -2435.10 -2472.30
Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00
SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92]
SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] COMS1 COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19]
Ver 1.0
5/54
2007/01/29
ST7576
PAD NO. PIN Name
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
X -2509.50 -2546.70 -2583.90 -2621.10 -2658.30 -2695.50 -2695.50 -2658.30 -2621.10 -2583.90 -2546.70 -2509.50 -2472.30 -2142.72 -2083.42 -2024.11 -1964.81 -1905.50 -1846.19 -1786.89 -1727.58 -1668.28 -1608.97 -1549.67 -1490.36 -1431.06 -1371.75 -1312.45 -1253.14 -1193.84
Y 293.00 293.00 293.00 293.00 293.00 293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50
PAD NO. PIN Name
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
X -1134.54 -1075.23 -1015.92 -956.62 -897.32 -838.01 -778.70 -719.40 -660.09 -600.79 -541.48 -482.18 -422.88 -363.57 -304.27 -244.96 -185.66 -126.35 -67.05 -7.74 51.56 110.87 170.17 229.47 288.78 348.09 407.39 539.23 598.53 657.84
Y -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50
COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[32] COM[31] COM[30] COM[29] COM[28] COM[27] COM[26] VDX2O VDX2O VDX2O VSS2 T11 T12 BR CP TMX TMY PS2 PS1 PS0 VMO VMO VMO VSS2
VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 RESB CSB RWR ERD A0 VDD1 D7 D6 D5 D4 D3 D2 D1 D0 OSC VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1
Ver 1.0
6/54
2007/01/29
ST7576
PAD NO. PIN Name
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
X 717.15 788.45 835.10 868.40 901.70 935.00 973.80 1012.60 1045.90 1079.20 1112.50 1158.81 1218.11 1277.42 1336.72 1396.03 1455.33 1514.64 1581.08 1640.38 1699.69 1759.00 1818.30 1877.60 1936.91 1999.36 2058.67 2117.98 2177.28 2236.58
Y -311.50 -311.50 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -309.75 -309.75 -309.75 -309.75 -309.75 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50
PAD NO. PIN Name
241 242 243 244 245 246 247 248 249 250
X 2295.89 2355.20 2435.10 2472.30 2509.50 2546.70 2583.90 2621.10 2658.30 2695.50
Y -311.50 -311.50 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00
VSS1 VRS T1 T2 T3 T4 T0 T5 T6 T7 T8 VGO VGO VGI VGI VGI VGI VGS V0O V0O V0I V0I V0I V0I V0S XV0O XV0O XV0I XV0I XV0I
XV0I XV0S COMS2 COM[60] COM[61] COM[62] COM[63] COM[64] Reserved Reserved
Ver 1.0
7/54
2007/01/29
ST7576
66 Duty (TMY=1)
PAD NO. PIN Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
X 2695.50 2658.30 2621.10 2583.90 2546.70 2509.50 2472.30 2435.10 2397.90 2360.70 2323.50 2286.30 2249.10 2211.90 2174.70 2137.50 2100.30 2063.10 2025.90 1988.70 1951.50 1914.30 1877.10 1839.90 1802.70 1765.50 1728.30 1665.39 1632.39 1599.39
Y 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 282.75 282.75 282.75
PAD NO. PIN Name
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
X 1566.39 1533.39 1500.39 1467.39 1434.39 1401.39 1368.39 1335.39 1302.39 1269.39 1236.39 1203.39 1170.39 1137.39 1104.39 1071.39 1038.39 1005.39 972.39 939.39 906.39 873.39 840.39 807.39 774.39 741.39 708.39 675.39 642.39 609.39
Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75
COM[5] COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] SEG[0] SEG[1] SEG[2]
SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32]
Ver 1.0
8/54
2007/01/29
ST7576
PAD NO. PIN Name
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
X 576.39 543.39 510.39 477.39 444.39 411.39 378.39 345.39 312.39 279.39 246.39 213.39 180.39 147.39 114.39 81.39 48.39 15.39 -17.60 -50.60 -83.60 -116.60 -149.60 -182.60 -215.60 -248.60 -281.60 -314.60 -347.60 -380.60
Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75
PAD NO. PIN Name
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
X -413.60 -446.60 -479.60 -512.60 -545.60 -578.60 -611.60 -644.60 -677.60 -710.60 -743.60 -776.60 -809.60 -842.60 -875.60 -908.60 -941.60 -974.60 -1007.60 -1040.60 -1073.60 -1106.60 -1139.60 -1172.60 -1205.60 -1238.60 -1271.60 -1304.60 -1337.60 -1370.60
Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75
SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62]
SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92]
Ver 1.0
9/54
2007/01/29
ST7576
PAD NO. PIN Name
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
X -1403.60 -1436.60 -1469.60 -1502.60 -1535.60 -1568.60 -1601.60 -1634.60 -1667.60 -1728.30 -1765.50 -1802.70 -1839.90 -1877.10 -1914.30 -1951.50 -1988.70 -2025.90 -2063.10 -2100.30 -2137.50 -2174.70 -2211.90 -2249.10 -2286.30 -2323.50 -2360.70 -2397.90 -2435.10 -2472.30
Y 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 282.75 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00 293.00
PAD NO. PIN Name
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
X -2509.50 -2546.70 -2583.90 -2621.10 -2658.30 -2695.50 -2695.50 -2658.30 -2621.10 -2583.90 -2546.70 -2509.50 -2472.30 -2142.72 -2083.42 -2024.11 -1964.81 -1905.50 -1846.19 -1786.89 -1727.58 -1668.28 -1608.97 -1549.67 -1490.36 -1431.06 -1371.75 -1312.45 -1253.14 -1193.84
Y 293.00 293.00 293.00 293.00 293.00 293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50
SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] COMS1 COM[64] COM[63] COM[62] COM[61] COM[60] COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45]
COM[44] COM[43] COM[42] COM[41] COM[40] COM[39] COM[32] COM[33] COM[34] COM[35] COM[36] COM[37] COM[38] VDX2O VDX2O VDX2O VSS2 T11 T12 BR CP TMX TMY PS2 PS1 PS0 VMO VMO VMO VSS2
Ver 1.0
10/54
2007/01/29
ST7576
PAD NO. PIN Name
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
X -1134.54 -1075.23 -1015.92 -956.62 -897.32 -838.01 -778.70 -719.40 -660.09 -600.79 -541.48 -482.18 -422.88 -363.57 -304.27 -244.96 -185.66 -126.35 -67.05 -7.74 51.56 110.87 170.17 229.47 288.78 348.09 407.39 539.23 598.53 657.84
Y -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50
PAD NO. PIN Name
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
X 717.15 788.45 835.10 868.40 901.70 935.00 973.80 1012.60 1045.90 1079.20 1112.50 1158.81 1218.11 1277.42 1336.72 1396.03 1455.33 1514.64 1581.08 1640.38 1699.69 1759.00 1818.30 1877.60 1936.91 1999.36 2058.67 2117.98 2177.28 2236.58
Y -311.50 -311.50 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -307.75 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -309.75 -309.75 -309.75 -309.75 -309.75 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50 -311.50
VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 RESB CSB RWR ERD A0 VDD1 D7 D6 D5 D4 D3 D2 D1 D0 OSC VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1
VSS1 VRS T1 T2 T3 T4 T0 T5 T6 T7 T8 VGO VGO VGI VGI VGI VGI VGS V0O V0O V0I V0I V0I V0I V0S XV0O XV0O XV0I XV0I XV0I
Ver 1.0
11/54
2007/01/29
ST7576
PAD NO. PIN Name
241 242 243 244 245 246 247 248 249 250
X 2295.89 2355.20 2435.10 2472.30 2509.50 2546.70 2583.90 2621.10 2658.30 2695.50
Y -311.50 -311.50 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00 -293.00
XV0I XV0S COMS2 COM[4] COM[3] COM[2] COM[1] COM[0] Reserved Reserved
Ver 1.0
12/54
2007/01/29
1 COM59 .......................................... 244 COM60 243 COMS 242 XV0S 238~241 XV0I 236~237 XV0O 235 V0S 231~234 V0I 229~230 V0O 228 VGS 224~227 VGI 222~223 VGO 221 T8 220 T7 219 T6 218 T5 217 T0 216 T4 215 T3 214 T2 213 T1 212 VRS 208~211 VSS1 204~207 VSS2 203 OSC 202 D0 201 D1 200 D2 199 D3 198 D4 197 D5 196 D6 195 D7 194 VDD1 193 A0 192 RD 191 WR 190 CSB 189 RESB 185~188 VDD2 181~184 VDD1 180 VSS2 179 VMO 178 VMO 177 VMO 176 PS0 175 PS1 174 PS2 173 TMY 172 TMX 171 CP 170 BR 169 T12 168 T11 167 VSS2 164~166 VDX2 27 COM33 28 SEG0 ............................................. 129 SEG101 130 COMS 131 COM0 ............................................. 163 COM26 156 COM25 ...... 157 COM32 18 17 16 ......
250 RESERVATION 249 RESERVATION
XV0 V0 C=1.0uF VG
789
A0 /RD /WR CSB RESB 2345 6 VDD 1
4. BLOCK DIAGRAM
ST7576
SYSTEMSIDE
FPCSIDE
ITOSIDE
Ver 1.0
13/54
14 13 12 11 10
D0 D1 D2 D3 D4 D5 D6 D7
Fig 3 Block diagram
15
Vss
2007/01/29
ST7576
5. PINNING DESCRIPTIONS
Pin Name
Lcd driver outputs LCD segment driver outputs This display data and the M signal control the output voltage of segment driver. Segment drover output voltage Display data Frame Normal display Reverse display SEG0 to SEG101
I/O
Description
No. of Pins
O
H H L L
H L H L
VG VSS VSS VG
VSS VG VG VSS
102
COM0 to COM64
O
Power save mode VSS VSS LCD column driver outputs This internal scanning data and M signal control the output voltage of common driver. Common drover output voltage Display data Frame Normal display Reverse display H H XV0 H L V0 L H VM L L VM Power save mode VSS Common output for the icons The output signals of two pins are same. When not used, this pin should be left open. Microprocessor interface select input pin PS2 PS1 PS0 State " L " " L " " L " 4 Pin-SPI MPU interface " H " " L " " L " 3 Pin-SPI MPU interface " L " " H " " L " 8080-series parallel MPU interface " H " " H " " L " 6800-series parallel MPU interface "H" "H" " H " I2C interface Chip select input pins Data/instruction I/O is enabled only when CSB is "L". When chip select is non-active, DB0 to DB7 is high impedance. There is no CSB pin in I2C interface, so this pin can fix to " H" Reset input pin When RESB is "L", initialization is executed. It determines whether the data bits are data or a command. A0="H": Indicates that D0 to D7 are display data. A0="L": Indicates that D0 to D7 are control data. There is no A0 pin in three line or I2C interface, so this pin can fix to " H"
65
COMS
O
2
MICROPROCESSOR INTERFACE
PS[2:0]
I
3
CSB
I
1
RESB
I
1
A0
I
1
Ver 1.0
14/54
2007/01/29
ST7576
Read/Write execution control pin (PS[0:1]=[L:H]) PS2 H RWR I L 8080-series /WR MPU type 6800-series /WR(R/W) R/W Description Read/Write control input pin R/W="H": read R/W="L": write Write enable clock input pin The data on D0 to D7 are latched at the rising edge of the /WR signal
1
When in the serial interface must fix to "H" Read/Write execution control pin (PS[0:1]=[L:H]) PS2 MPU Type /RD (E) Description Read/Write control input pin R/W="H": When E is "H", D0 to D7 are in an output status. R/W="L": The data on D0 to D7 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is "L", D0 to D7 are in an output status.
ERD
I
H
6800-series
E
1
L
8080-series
/RD
When in the serial interface must fix to " H" When using 8-bit parallel interface : 6800 . 8080 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When chip select is not active, D0 to D7 is high impedance. When using serial interface: 4-LINE.3-LINE D7: serial input clock (SCLK) ; D6: serial input data (SDA) D5: command/data selection (A0) ; D4: chip select pin(CSB) D3,D2.D1.D0: must fix to " H" When using 3-line A0 must fix to "H"
D7(SCLK) D6(SDA) D5(A0) D4(CSB) D3 to D0
I/O
D7 to D6 (SA) D5 to D4(X) D3 to D2 (SDA_OUT) D1 (SDA_IN) D0 (SCLK)
When using I2C interface D7: serial clock input (SCLK) D6: serial input data (SDA_IN) D3, D2: (SDA_OUT) serial data acknowledge for the I2C interface. By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully 2 I C interface compatible. Having the acknowledge output separated from the serial data line is advantageous in chip on glass (COG) applications. In COG application where the track resistance from the SDA_OUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance. It is possible the during the acknowledge cycle the ST7576 will not be able to create a valid logic 0 level. By splitting the SDA_IN input from the SDA_OUT output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDA_OUT pad to the system SDA line to guarantee a valid low level. D6, D3,D2 must be connected together (SDA) D4, D5: must fix to " H" D0, D1: Is slave address (SA0,SA1), must fix to "H" or "L" Chip select input pins "CSB" not used must fix to "H"
8
Ver 1.0
15/54
2007/01/29
ST7576
LCD DRIVER SUPPLY When the on-chip oscillator is used, this input must be connected to VDD1. An external clock signal, if used, is connected to this input. If the oscillator and external clock are both inhibited by connecting the OSC pin to VSS the display is not clocked and may be left in a DC state. To avoid this, the chip should always be put into Power Down Mode before stopping the clock.
OSC
I
1
Power Supply Pins VSS1 VSS2 VDX2 Power Power Power Digital ground: must be connected with VSS2 Analog ground: must be connected with VSS1 Testing mode power. Must be floating. Digital Supply voltage:1.8V~3.3V The 2 supply rails VDD1 and VDD2 could be connected together. Digital Option pin must connect to VDD1 to pull high Analog Supply voltage:1.8V~3.3V The 2 supply rails VDD1 and VDD2 could be connected together. Negative LCD driver supply voltage XV0O, XV0I & XV0S should be separated in ITO layout. XV0O, XV0I & XV0S should be connected together in FPC layout. Positive LCD driver supply voltage V0 VG VM VSS XV0 V0O, V0I & V0S should be separated in ITO layout. V0O, V0I & V0S should be connected together in FPC layout. LCD driving voltage for segments VGO, VGI & VGS should be separated in ITO layout. VGO, VGI & VGS should be connected together in FPC layout. VM output. LCD driving voltage for commons. Monitor Voltage Regulator level, must be left open. 4 6 3
VDD1
Power
5
VDD2 XV0
Power Power
4 7
V0
Power
7
VG VMO VRS
Power Power Power
7 3 1
Ver 1.0
16/54
2007/01/29
ST7576
Configuration Pins CP I Set Booster stages. ("L"=4X; "H"=5X) CP pin set the default value of booster stages after reset , and booster stage can be changed by software instruction Set LCD bias ratio. ("L"=1/7; "H"=1/9) BR pin set the default value of bias ratio after reset , and bias ratio can be changed by software instruction Mirror X: SEG bi-direction selection TMX connect to VSS : normal direction (SEG0aSEG101) TMX connect to VDD : reverse direction (SEG101aSEG0) Mirror Y: COM bi-direction selection TMY connect to VSS (TMY=0): normal direction TMY connect to VDD (TMY=1): reverse direction See Pad Center Coordinates at page 3~10. Test Pin T0~T8 T11 T12 T T T Do NOT use. Reserved for testing. Must be floating Do NOT use. Reserved for testing. Must be pull high Do NOT use. Reserved for testing. Must be pull low 9 1 1 1
BR
I
1
TMX
I
1
TMY
I
1
ST7576 I/O PIN ITO Resister Limitation PIN Name PS[2:0], OSC, CP, BR, T11, T12 T0~T8, VRS, VDX2, TMX, TMY VDD1, VDD2, VSS V0(V0I, V0O, V0S), VG(VGI, VGO, VGS), XV0(XV0I, XV0O, XV0S), VM A0, /WR, /RD, CSB, D7...D0 RESB ITO Resister No Limitation Floating <100 <500 <1K RESB<10K
Ver 1.0
17/54
2007/01/29
ST7576
6. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE Chip Select Input There is CSB pin for chip selection. The ST7576 can interface with an MPU when CSB is "L". When CSB is "H", these pins are set to any other combination, A0, /RD(E), and /WR(R/W) inputs are disabled and D0 to D7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface ST7576 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial interface is determined by PS [0:2] pin as shown in table 1. Table 1. Parallel/Serial Interface Mode PS2 "L" "H" "L" "H" "H" PS1 "L" "L" "H" "H" "H" PS0 "L" "L" "L" "L" "H" State 4 Pin-SPI MPU interface 3 Pin-SPI MPU interface 8080-series parallel MPU interface 6800-series parallel MPU interface I2C interface
Parallel Interface The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS2 as shown in table 2. The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in table 3. Table 2. Microprocessor Selection for Parallel Interface PS0 CSB A0 /RD (E) /WR (R/W) D0 to D7 MPU bus L CSB A0 E R/W D0 to D7 6800-series L CSB A0 /RD /WR D0 to D7 8080-series
PS2 H L
PS1 H H
Table 3. Parallel Data Transfer 6800-series 8080-series Description E R/W /RD /WR A0 (/RD) (/WR) (E) (R/W) H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction) NOTE: When /RD (E) pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, /WR(R/W) as in case of 6800-series mode. Common Serial Interface Serial Mode 4-line SPI interface 3-line SPI interface I2C interface
PS2 L H H
PS1 L L H
PS0 L L H
CSB CSB CSB Not Used Fix to "H"
A0 Used Not Used Fix to "H" Not Used Fix to "H"
Ver 1.0
18/54
2007/01/29
ST7576
PS2= "L", PS1= "L", PS0= "L": 4-line SPI interface When the ST7576 is active (CSB="L"), serial data (D6) and serial clock (D7) inputs are enabled. When CSB is "High", the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication is controlled by the register selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be instruction when A0 is low. The read feature is not supported in this mode. Serial data on SDA (D6) is latched at the rising edge of serial clock on SCLK (D7). After the eighth serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access.
129 SEG101
156 COM25 .. . .. . 157 COM32
156 CO M25 .. . .. . 157 CO M32
130 COMS
131 COM0
27 COM33
28 SE G0
1 COM59
. . .. .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. .. . .. .. .
. .. . .. .. .. . .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. .
. .. .. . .. .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. .
204~207 VSS2
208~211 VSS1
236~237 XV0O
164~166 VDX2
222~223 VGO
229~230 V0O
238~241 XV0I
181~184 VDD1
185~188 VDD2
224~227 VGI
231~234 V0I
242 XV0S
196 SDA(D6)
198 CSB(D4)
228 VGS
250 R ESERVA TI N O
19 5 SCLK( D7)
235 V0S
2 RESE RVATION 49
IT O
FPC
SYSTEM
PS2= "L", PS1= "L", PS0= "H": 3-line SPI interface When ST7576 is active (CSB="L"), SDA-out, SDA-in and SCL inputs are enabled. When ST7576 is not active (CSB="H"), the internal 8-bit shift register and the 3-bit counter are reset. The A0 pin is not available in this mode. Before issuing serial data, an A0 bit is required to indicate the access is data or instruction. The read feature is not supported in this mode except ID code read feature. Serial data on SDA (D6) is latched at the rising edge of serial clock on SCLK (D7). After the eighth serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access.
129 S EG 101 13 0 CO MS 131 CO M0 27 CO M33 28 S EG 0 1 CO M59 . .. . .. .. .. . .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. . . .. .. . .. .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. .
IT
163 COM26
163 CO M26
197 A0(D5)
244 COM60
189 RE SB
243 COMS
. . .. ..
S ID E
S ID E
S ID E
. . .. .. .. . .. .. .. . .. .. . .. .. .. . .. .. .. . .. .. . .. .. .
167 V SS2
167 V SS 2
180 V SS2
194 VDD1
172 TMX
173 TMY
174 PS2
175 PS1
176 PS0
177 VMO
178 VMO
179 VMO
203 OSC
212 VRS
168 T11
169 T12
170 BR
171 CP
191 WR
192 RD
213 T1
214 T2
215 T3
216 T4
217 T0
218 T5
219 T6
220 T7
221 T8
190 X
193 X
199 X
200 X
201 X
202 X
1
2 RESB
3 SCLK
4
5
6
7
10
8
9
VDD
Fig 4 4-line SPI Timing
SDA
CSB
204~207 V SS 2
Vss
VG
XV0
A0
V0
C
= 1 .0 u F
208~211 V SS 1
236~237 XV0O
164~166 V DX 2
222~223 V G O
229 ~230 V0O
238~241 X V0I
181~184 V DD 1
185~188 V DD 2
224~227 V G I
231~ 234 V0I
1 96 SD A(D 6)
1 98 CS B(D 4)
228 V G S
242 XV0 S
2 50 RE E ATI ON S RV
195 S CLK( D7)
235 V0S
249 RE S RV I N E AT O
244 C OM60
180 V SS 2
189 R ESB
194 V DD 1
243 CO MS
. . .. ..
172 TMX
173 TMY
174 PS2
175 PS1
176 PS 0
177 VMO
178 VMO
179 VMO
203 O SC
212 V RS
168 T11
169 T12
170 BR
171 C P
191 WR
192 R D
190 X
213 T1
214 T2
215 T3
216 T4
217 T0
218 T5
219 T6
220 T7
221 T8
193 X
197 X
199 X
200 X
201 X
2X 02
O
S
ID
E
F
P
C
S
ID
E
S
Y
S
T
E
M
S
ID
E
1
2
3
4
5
6
7
8
9
R ESB
SC LK
V DD
Fig 5 3-line SPI Timing
SD A
C SB
Vss C = 1 .0
VG u F
XV0
V0
Ver 1.0
19/54
2007/01/29
ST7576
PS2= "H", PS1= "H", PS0= "H": I2C Interface The I2C interface receives and executes the commands sent via the I2C Interface. It also receives RAM data and sends it to the RAM. The I2C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Fig.6. START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.7. SYSTEM CONFIGURATION The system configuration is illustrated in Fig.8. - Transmitter: the device, which sends the data to the bus - Receiver: the device, which receives the data from the bus - Master: the device, which initiates a transfer, generates clock signals and terminates a transfer - Slave: the device addressed by a master - Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message - Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted - Synchronization: procedure to synchronize the clock signals of two or more devices. ACKNOWLEDGE Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C Interface is illustrated in Fig.9.
129 SE G101 156 COM25 ...... 157 COM32 131 COM0 130 COMS 27 COM33 1 COM59 28 SEG0 . .. . . . . . . .. . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .. . . . . . .
. . . . . . . .. . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . .
204~207 VS S2
208~211 VS S1
164~166 VDX2
236~237 X V0O
222~223 V GO
229~230 V0O
238~241 XV0I
181~184 V DD1
185~188 V DD2
224~227 VGI
231~234 V0I
242 X V0S
196 SDA_IN(D6)
199 SDA _O UT(D 3)
200 SDA _O UT(D 2)
228 V GS
250 RES ERVATION
19 5 SCLK(D7 )
201 SA1(D1)
235 V0S
2 RESERVA TI N 49 O
IT O
FPC
SY STE M
163 COM26
20 2 SA0 (D0 )
244 COM60
......
189 RESB
194 VDD1
243 COMS
S ID E
S ID E
S ID E
Fig 7 Definition of START and STOP conditions
167 VSS2
177 VMO
178 VMO
179 VMO
180 VSS2
172 TMX
173 TMY
174 PS2
175 PS1
176 PS 0
203 OSC
212 VRS
168 T11
169 T12
170 BR
171 CP
191 WR
192 RD
190 X
213 T1
214 T2
215 T3
216 T4
217 T0
218 T5
219 T6
220 T7
221 T8
193 X
197 X
198 X
1
2 RESB
3 SCLK
4
6
7
8
9
VDD
Fig 6 Bit transfer
SDA
V ss
XV0
C = 1 .0 u F
VG
V0
Ver 1.0
20/54
2007/01/29
ST7576
Fig 8 System configuration
Fig 9 Acknowledgement on the I2C Interface I2C Interface protocol The ST7576 supports command, data write addressed slaves on the bus. Before any data is transmitted on the I2C Interface, the device, which should respond, is addressed first. Four 7-bit slave addresses (0111100,0111101, 0111110 and 0111111) are reserved for the ST7576. The least significant bit of the slave address is set by connecting the input SA0 and SA1 to either logic 0 or logic 1 (VDD1). The I2C Interface protocol is illustrated in Fig.10. The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C Interface transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and A0, and a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes will follow. The state of the A0 bit defines whether the data byte is interpreted as a command or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended ST7576 device. If the A0 bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the bus master issues a STOP condition (P). If no acknowledge is generated by the master after a byte, the driver stops transferring data to the master.
Ver 1.0
21/54
2007/01/29
ST7576
R/W Co
Co
0 1
Fig 10 I2C Interface protocol Last control byte to be sent. Only a stream of data bytes is allowed to follow. This stream may only be terminated by s STOP or RE-START condition. Another control byte will follow the data byte unless a STOP or RE-START condition is received.
Data Transfer The ST7576 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Fig. 11. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Fig. 12. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
MPU signal A0 /WR D0 to D7 Internal signals /WR BUS HOLDER COLUMN ADDRESS N D(N) N D(N+1) N+1 D(N+2) N+2 D(N+3) N+3 N D(N) D(N+1) D(N+2) D(N+3)
Fig 11 Write Timing
Ver 1.0
22/54
Co
2007/01/29
ST7576
MPU signal A0 /W R /RD D0 to D7 Internal signals /WR /RD BUS HOLDER COLUMN ADDRESS N N D(N) D(N) D(N+1) D(N+1) D(N+2) D(N+2) N Dummy D(N) D(N+1)
Fig 12 Read Timing
DISPLAY DATA RAM (DDRAM) The ST7576 contains a 66X102 bit static RAM that stores the display data. The display data RAM store the dot data for the LCD. It has a 66(8 pageX8 bit +1 pageX1 bit +1 pageX1 bit) X 102 . There is a direct correspondence between X-address and column output number. It is 66-row by 102-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines (0~63 COM) and 8th page with single line (D0)(64COM) and 9th page with a single line (D0)(COMS (ICOM). Data is read from or written to the 8 lines of each page directly through D0 to D7. The display data of D0 to D7 from the microprocessor correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. Page Address Circuit This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 9 is a special RAM area for the icons and display data D0 is only valid. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in Fig. 10. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 102-bit RAM data to the display data latch circuit. When icon is selected by setting icon page address, display data of icons are not scrolled because the MPU cannot access Line Address of icons.
Ver 1.0
23/54
2007/01/29
ST7576
Column Address Circuit Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in figure16. The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. ADDRESSING Data is downloaded in bytes into the RAM matrix of ST7576. The display RAM has a matrix of 66 by 102 bits. The address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101),Y 0 to 9 (1001) .Addresses outside these ranges are not allowed.In vertical addressing mode (V=1) the Y address increments after each byte. After the last Y address (Y = 8), Y wraps around to 0 and X increments to address the next column.In horizontal addressing mode (V=0) the X address increments after each byte. After the last X address(X = 101) X wraps around to 0 and Y increments to address the next row.After the very last address (X = 101, Y = 8) the address pointers wrap around to address (X = 0, Y =0) Data structure
D0
LSB
D7
MSB
LSB 1 bit 0 Xaddress
Fig13 RAM format
10 1
0 1 2 3 4 5 6 7 8 9
Ver 1.0
24/54
2007/01/29
Yaddress
ST7576
Data structure
0 1 2 3 4 5 6 7 8 0
9 10 11 12 13 14 15 16 17
18 19 20 21 22 23 24 25 26
0 1 2 3 4 5 6 7 8 9
917 101
X-address
Fig14 Sequence of writing data bytes into RAM with vertical addressing (V=1)
012 102103104 204205206 306307308 408409410 510511512 612613614 714715716 816817818 0 X-address
917 101
0 1 2 3 4 5 6 7 8 9
Fig15 Sequence of writing data bytes into RAM with horizontal addressing (V=0)
Ver 1.0
25/54
Y-address
2007/01/29
ST7576
Page Address Dat D3 D2 D1 D0 a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00 01 02 03 04 05 06 07 08 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
When the common output is normal
COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1
0
0
0
Page 8 D0 5D 5E 5F 60 61 62 63 64 65 0 MX Column address
S100
S101
Fig.16 Display Data RAM Map (66 COM)
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LCD Out
S93
S94
S95
S96
S97
S98
S99
S0
S1
S2
S3
S4
S5
S6
S7
S8
D0
5D
5E
5F
65
64
63
62
61
60
08
07
06
05
04
03
02
01
00
Regardless of the display start line address, 1/65duty => 64th line,
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Partial Display on LCD The ST7576 realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages.
Fig 17 Reference Example for Partial Display
Fig 18 Partial Display (Partial Display Duty=17, initial COM0=0)
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-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Fig 19 Moving Display (Partial Display Duty=17, Initial COM0=8)
Liquid Crystal Driver Power Circuit The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction.
External Power Components
Fig 20 Power Circuit
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7. RESET CIRCUIT
Setting RESB to "L" or Reset instruction can initialize internal function. When RESB becomes "L", following procedure is occurred. Page address: 0 Column address: 0 Display control: Display blank COM Scan Direction MY: 0 SEG Select Direction MX: 0 DO=0 Oscillator: OFF Power down mode (PD = 1) normal instruction set (H[1:0] = 00) Display blank (E = D = 0) Address counter X [6:0] = 0, Y [3:0] = 0 Bias system: depend on Hardware (BR) setting Booster stage: depend on Hardware (CP) setting V0 is equal to 0; the HV generator is switched off (VOP [6:0] = 0) After power-on, RAM data are undefined While RESB is "L" or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at D0. After D0 becomes "L", any instruction can be accepted. RESB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESB is essential before used.
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8. INSTRUCTION TABLE
INSTRUCTION H=0 or 1 NOP Function set 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 D6 0 1 1 1 D5 0 0 0 1 D4 0 0 1 1 D3 0 PD X DP2 D2 0 V X DP1 D1 0 H PS DP0 D0 No operation Power-down; entry mode; Partial screen enable Set display part for partial screen mode Write data to RAM A0
WR (R/W)
COMMAND BYTE DESCRIPTION D7 D6 D5 D4 D3 D2 D1 D0
Partial screen mode 0 Display part Write data 0 1
INSTRUCTION H=0 Set VLCD range Display control Set Y address of RAM Set X address of RAM H=1 Reserved Reserved Bias system Reserved Set VOP
A0
WR (R/W)
COMMAND BYTE DESCRIPTION D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 1 X6
0 0 0 X5
1 0 0 X4
0 1 Y3 X3
0 D Y2 X2
0 0 Y1 X1
PRS VLCD range L/H select E Y0 X0 Sets display configuration Sets Y address of RAM 0Y9 Sets X address of RAM 0X101
0 0 0 0 0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 VOP6
0 0 0 X VOP5
0 0 1 X VOP4
0 0 0 X VOP3
0 0 BS2 X VOP2
0 1 BS1 X VOP1
X X BS0 X
Do not use Do not use Sets bias system (BSx) Do not use(reserved for test)
VOP0 Write VOP to register
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9. INSTRUCTION DESCRIPTION
Function Set
A0 0 Flag
WR(R/W)
0
D7 0
D6 0
D5 1
D4 0
D3 0
D2 PD
D1 V
D0 H
PD
H
Description PD=0:chip is active PD=1:chip is in power down mode All LCD outputs at VSS (display off), bias generator and V0 generator off, VOUT can be disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data can be written. H are used to select different instruction block Follow the instruction table
Partial screen mode A0 0 Flag PS
WR(R/W)
0
D7 0
D6 0
D5 1
D4 0
D3 1
D2 X
D1 X
D0 PS
Description Full display mode or partial screen mode selection PS=0: Full display mode with MUX 1:66 PS=1: Partial screen mode with MUX 1:17
Display part A0 WR(R/W) 0 0 Flag 0 0 0 0 1 1
D7 0 Status 0 0 1 1 0 0
D6 0
D5 1
D4 1
D3 1
D2 DP2
D1 DP1
D0 DP0
DP2 DP1 DP0
0 1 0 1 0 1
Description Display common DDRAM position Start from common 0 Start from page 0 Start from common 8 Start from page 1 Start from common 16 Start from page 2 Start from common 24 Start from page 3 Start from common 32 Start from page 4 Start from common 40 Start from page 5
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Read data 8-bit data of Display Data from the RAM location specified by the column address and page address can be read to the microprocessor. D7 D6 D5 D4 D3 D2 D1 D0 A0 WR(R/W) 1 1 Read data
Write data 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 1
WR(R/W)
D7
D6
D5
0
D4 D3 Write data
D2
D1
D0
H="0"
Set VOP range
VOP range L/H select A0 WR(R/W) D7 D6 0 0 0 0 PRS=0: VOP programming range LOW PRS=1: VOP programming range HIGH D5 0 D4 1 D3 0 D2 0 D1 0 D0 PRS
Display Control
This bits D and E selects the display mode. A0 0 Flag
WR(R/W)
0
D7 0
D6 0
D5 0
D4 0
D3 1
D2 D
D1 0
D0 E
D,E
Description D E The bits D and E select the display mode. 0 0 Display blank 1 0 Normal display 0 1 All display segments on 1 1 Inverse video mode
Set Y address of RAM
Y [3:0] defines the Y address vector address of the display RAM. A0 WR(R/W) D7 D6 D5 D4 D3 0 0 0 1 0 0 Y3 Y3 0 0 0 0 0 0 0 0 1 1 Y2 0 0 0 0 1 1 1 1 0 0 Y1 0 0 1 1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 0 1 0 1 CONTENT Page0 (display RAM) Page1 (display RAM) Page2 (display RAM) Page3 (display RAM) Page4 (display RAM) Page5 (display RAM) Page6 (display RAM) Page7 (display RAM) Page8 (display RAM) Page9 (display RAM) D2 Y2 D1 Y1 D0 Y0
ALLOWED X-RANGE 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101
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Set X address of RAM
The X address points to the columns. The range of X is 0...101. D7 D6 D5 D4 A0 WR(R/W) 0 0 1 X6 X5 X4 X6 0 0 0 0 : 1 1 1 1 H="1" X5 0 0 0 0 : 1 1 1 1 X4 0 0 0 0 : 0 0 0 0 X3 0 0 0 0 : 0 0 0 0 X2 0 0 0 0 : 0 0 1 1 X1 0 0 1 1 : 1 1 0 0 D3 X3 X0 0 1 0 1 : 0 1 0 1 D2 X2 D1 X1 D0 X0
Column address 0 1 2 3 : 98 99 100 101
System Bias
Select LCD bias ratio of the voltage required for driving the LCD. A0 WR(R/W) D7 D6 D5 D4 D3 0 0 0 0 0 1 0 BS2 BS1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 LCD bias voltage Symbol V0 V3 V4 VGND XV0 BS0 0 1 0 1 0 1 0 1 Bias 11 10 9 8 7 6 5 4 D2 BS2 D1 BS1 D0 BS0
Recommend Duty 1:100 1:81 1:65/1:68 1:49 1/40:1/36 1/24 1:18/1:16 1:10/1:9/1:8
Bias voltage for 1/9 bias V0 2/9 X V0 2/9 X V0 VSS -V0
Set VO value
A0 WR(R/W) D7 D6 D5 0 0 1 VOP6 VOP5 The operation voltage VLCD can be set by software. D4 VOP4 D3 VOP3 D2 VOP2 D1 VOP1 D0 VOP0
VOP=( a + VOPx*b )
(1)
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The maximum voltage that can be generated is depending on the VDD1 voltage and the display load current. Two overlapping VLCD ranges are selectable via the command "Booster control". For the LOW (PRS=0) range a=a1 and for the HIGH (PRS=1) range a=a2 with steps equal to "b" in both ranges. Note that the charge pump is turned off if VOP [6;0] and the bit PRS are all set to zero
* The Vop must be operated in the range of 4V to 9.5V for the normal or partial display mode application, so that customer have some range(<4V; >9.5V) to adjust contrast by themselves.
Table 4 Typical values for parameter for the HV-Generator programming SYMBOL a1 a2 b VALUE 2.94(PRS=0) 6.75(PRS=1) 0.03 UNIT V V V
VL2
Charge pump off
b a2 a1+b 01 02 03 04 05 06 ..... 7D 7E 7F 00 01 02 03 04 05 06 ..... 7D 7E 7F
00
LOW(PRS=0)
HIGH(PRS=1)
VOP [6:0](programmed) {00 hex... 7F hex} Fig21 VOP programming of ST7576
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10. COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON(VDD-VSS) Keeping the /RESB Pin="L"
Waiting for Stabilizing the Power Release the reset state. (/RESB pin="H") Waiting reset circuit stablized(>1ms)
Function set PD=0 ,V=0 , H=1 SET Bias system SET V0 Function set PD=0 , V=0 , H=0 Set VLCD Range(PRS) Display control D=1 E=0 (Normal) Set X , Y address
End of Initialization
Fig 22 Initializing with the Built-in Power Supply Circuits
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11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Power Supply Voltage Power supply voltage LCD Power supply voltage LCD Power supply voltage LCD Power driving voltage Operating temperature Storage temperature VDD1 VDD2 V0 XV0-VG VG, VM TOPR TSTR Symbol Conditions -0.3 ~ 3.6 -0.3 ~ 3.6 -0.3~15 -15~0.3 -0.3 ~ VDD2 -30 to +85 -65 to +150 V V V V V C C Unit
Fig 23 Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. Insure that the voltage levels of VG, VM, VSS, and XV0 are always such that V0 VDD2 VG > VM > VSS XV0
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12. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices").
13. DC CHARACTERISTICS
VDD1 = 1.8V to 3.3V; VSS = 0V; Tamb = -30 to +85; unless otherwise specified. Item Symbol Condition Rating Min. 1.8 Typ. Max. -- 3.3 Units Applicable Pin VDD1
Operating Voltage (1)
VDD1
V
Operating Voltage (2) High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current
VDD2 VIHC VILC VOHC VOLC ILI ILO
(Relative to VSS)
2.4 0.7 x VDD1 VSS
-- -- -- -- -- -- -- 0.7
3.3 VDD1 0.3 x VDD1 VDD1 0.2 x VDD1 1.0 3.0 --
V V V V V A A
VDD2
IOUT=1mA; VDD1=1.8V IOUT=1mA; VDD1=1.8V
0.8 x VDD1 VSS -1.0 -3.0
Vop= 9.0 V Liquid Crystal Driver ON Resistance RON Ta = 25C V=0.9V VG = 2.0 V V=0.2V
--
K -- 0.7 --
COMn SEGn
Frame frequency
FR
FR default (1,0,0)
71
75
79
Hz
Item Internal Power Positive power for common driver Negative power for common driver
Symbol
Condition
Rating Min. 3 Typ. -- Max. 12
Units Applicable Pin
V0
(V0-XV0)
V
V0
XV0
(XV0-V0)
-3
--
-12
V
XV0
*Recommand: LCD Vop range is 4V-9.5V
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Dynamic consumption current: During Display, with Internal Power Supply ON, current consumed by whole IC (bare die). Test pattern Symbol Condition VDD = 3.0 V, ISS Booster X5 V0 - VSS = 9.0 V Bias=1/9 ISS Ta = 25C VDD = 3.0 V, Booster X5 ISS V0 - VSS = 9.0 V Bias=1/9 Data write frequency: 1M Hz -- uA -- 0.7 10 uA -- 110 150 uA Rating Min. Typ. Max. Units Notes
Display Pattern SNOW (static)
Power Down
Display Pattern SNOW (dynamic, 4-SPI)
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14. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
(VDD = 3.3V , Ta =-30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 10 80 350 70 50 120 50 60 10 -- 10 -- -- 70 50 Max. -- -- -- -- -- -- ns Units
A0
WR WR
RD
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(VDD = 2.8V , Ta =-30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 15 120 450 120 100 120 100 90 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100 ns Units
A0
WR WR
RD
(VDD = 1.8V , Ta =-30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 30 150 550 170 150 170 150 120 30 -- 10 -- -- 240 200 Max. -- -- -- -- -- -- ns Units
A0
WR WR
RD
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD1 as the reference. *3 tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level.
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System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
(VDD = 3.3V , Ta =-30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 10 80 240 70 50 70 130 60 10 -- 10 -- -- 70 50 Max. -- -- -- -- -- -- ns Units
RD
Ver 1.0
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(VDD = 2.8V , Ta =-30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 15 100 340 120 100 120 100 120 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100 ns Units
RD
(VDD = 1.8V , Ta =-30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 30 150 440 170 150 170 150 180 30 -- 10 Max. -- -- -- -- -- -- -- -- -- 240 200 ns Units
RD
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD1 as the reference. *3 tEWLW and tEWLR are specified as the overlap between CSB being "L" and E.
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SERIAL INTERFACE(4-Line Interface)
(VDD = 3.3V , Ta =-30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 120 60 60 20 90 20 10 20 120 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
CSB
(VDD = 2.8V , Ta =-30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 200 100 100 30 120 30 20 30 150 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
CSB
Ver 1.0
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(VDD=1.8V,Ta=-30~85) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 280 140 140 50 150 50 50 40 180 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
CSB
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD1 as the standard.
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SERIAL INTERFACE (3-Line Interface)
First bit
Last bit
(VDD=3.3V,Ta=-30~85) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 120 60 60 20 10 20 130 Max. -- -- -- -- -- -- -- ns Units
CSB
(VDD=2.8V,Ta=-30~85) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 180 90 90 30 20 30 160 Max. -- -- -- -- -- -- -- ns Units
CSB
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(VDD=1.8V,Ta=-30~85) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 240 120 120 60 50 40 190 Max. -- -- -- -- -- -- -- ns Units
CSB
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD1 as the standard.
SERIAL INTERFACE(I2C Interface)
(VDD=3.3V,Ta=-30~85) Item SCL clock frequency SCL clock low period SCL clock high period Data set-up time Data hold time SCL,SDA rise time SCL,SDA fall time Capacitive load represented by each bus line Setup time for a repeated START condition Start condition hold time Setup time for STOP condition Tolerable spike width on bus BUS free time between a STOP and START condition SCL SI SI Signal Symbol SCL SCL SCL SI SI SCL SCL FSCLK TLOW THIGH TSU;Data THD;Data TR TF Cb TSU;SUA THD;STA TSU;STO TSW TBUF Condition 1.3 0.6 100 0 Rating Min. Max. 400 0.9 Units KHz us us ns us ns ns pF us us us ns us
20+0.1Cb 300 20+0.1Cb 300 0.6 0.6 0.6 1.3 400 50
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15. RESET TIMING
tRW /RES
tR Internal status During reset Reset complete
(VDD = 3.3V , Ta = -30 to 85C ) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 1.5 Typ. -- -- Max. 1.5 -- Units us us
(VDD = 2.8V , Ta = -30 to 85C ) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 2.0 Typ. -- -- Max. 2.0 -- Units us us
(VDD = 1.8V , Ta = -30 to 85C ) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 3.0 Typ. -- -- Max. 3.0 -- Units us us
Ver 1.0
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250 RESERVATIO N
1 COM59
249 RESERVATIO N
......
..........................................
244 COM60 243 COMS 242 XV0S 238~241 XV0I 236~237 XV0O 235 V0S 231~234 V0I 229~230 V0O 228 VGS 224~227 VGI 222~223 VGO 221 T8 220 T7 219 T6 218 T5 217 T0 216 T4 215 T3 214 T2 213 T1 212 VRS 208~211 VSS1 204~207 VSS2 203 OSC 202 D0 201 D1 200 D2 199 D3 198 D4 197 D5 196 D6 195 D7 194 VDD1 193 A0 192 RD 191 WR 190 CSB 189 RESB 185~188 VDD2 181~184 VDD1 180 VSS2 179 VMO 178 VMO 177 VMO 176 PS0 175 PS1 174 PS2 173 TMY 172 TMX 171 CP 170 BR 169 T12 168 T11 167 VSS2 164~166 VDX2
18
XV0
17
V0
16
VG
28 SEG0
APPLICATION NOTE
.............................................
15
Vss
129 SEG101
130 COMS 131 COM0
A0 /RD /WR CSB RESB
2345 6
VDD
.............................................
ST7576
163 COM26 ...... 156 COM25
SYSTEM SIDE
FPC SIDE
ITO SIDE
1
157 COM32
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14 13 12 11 10
D0 D1 D2 D3 D4 D5 D6 D7
789
C=1.0uF
27 COM33
2007/01/29
250 RESERVATIO N
..........................................
244 COM60 243 COMS 242 XV0S 238~241 XV0I 236~237 XV0O 235 V0S 231~234 V0I 229~230 V0O 228 VGS 224~227 VGI 222~223 VGO 221 T8 220 T7 219 T6 218 T5 217 T0 216 T4 215 T3 214 T2 213 T1 212 VRS 208~211 VSS1 204~207 VSS2 203 OSC 202 D0 201 D1 200 D2 199 D3 198 D4 197 D5 196 D6 195 D7 194 VDD1 193 A0 192 RD 191 WR 190 CSB 189 RESB 185~188 VDD2 181~184 VDD1 180 VSS2 179 VMO 178 VMO 177 VMO 176 PS0 175 PS1 174 PS2 173 TMY 172 TMX 171 CP 170 BR 169 T12 168 T11 167 VSS2 164~166 VDX2
18
XV0
17 16
V0
VG
28 SEG0
.............................................
15 14 13 12 11 10 789
Vss
D0 D1 D2 D3 D4 D5 D6 D7 2345 6
C=1.0uF
27 COM33
129 SEG101
130 COMS 131 COM0
A0 /RD /WR CSB RESB 1
VDD
.............................................
ST7576
156 COM25
157 COM32
Ver 1.0
......
163 COM26
SYSTEM SIDE
FPC SIDE
ITO SIDE
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1 COM59
249 RESERVATIO N
......
250 RESERVATIO N
1 COM59
249 RESERVATIO N
..........................................
244 COM60 243 COMS 242 XV0S 238~241 XV0I 236~237 XV0O 235 V0S 231~234 V0I 229~230 V0O 228 VGS 224~227 VGI 222~223 VGO 221 T8 220 T7 219 T6 218 T5 217 T0 216 T4 215 T3 214 T2 213 T1 212 VRS 208~211 VSS1 204~207 VSS2 203 OSC
202 X
10 9 8
XV0
V0
28 SEG0
.............................................
Vss 7
195 SCLK(D7)
129 SEG101
130 COMS 131 COM0
ST7576
.............................................
SYSTEM SIDE
FPC SIDE
ITO SIDE
194 VDD1 193 X 192 RD 191 WR 190 X 189 RESB 185~188 VDD2 181~184 VDD1 180 VSS2 179 VMO 178 VMO 177 VMO 176 PS0 175 PS1 174 PS2 173 TMY 172 TMX 171 CP 170 BR 169 T12 168 T11 167 VSS2 164~166 VDX2 163 COM26 156 COM25 ...... 157 COM32
3456
201 X 200 X 199 X 198 CSB(D4) 197 A0(D5) 196 SDA(D6)
C=1.0uF
27 COM33
VG
CSB A0 SDA SCLK
RESB 2 1
VDD
Ver 1.0
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......
1 COM59
249 RESERVATIO N
..........................................
244 COM60 243 COMS 242 XV0S 238~241 XV0I 236~237 XV0O 235 V0S 231~234 V0I 229~230 V0O 228 VGS 224~227 VGI 222~223 VGO 221 T8 220 T7 219 T6 218 T5 217 T0 216 T4 215 T3 214 T2 213 T1 212 VRS 208~211 VSS1 204~207 VSS2 203 OSC
202 X
XV0 9
V0 8
28 SEG0
.............................................
Vss 6
195 SCLK(D7)
129 SEG101
130 COMS 131 COM0
.............................................
ST7576
163 COM26 156 COM25 ...... 157 COM32
SYSTEM SIDE
FPC SIDE
ITO SIDE
194 VDD1 193 X 192 RD 191 WR 190 X 189 RESB 185~188 VDD2 181~184 VDD1 180 VSS2 179 VMO 178 VMO 177 VMO 176 PS0 175 PS1 174 PS2 173 TMY 172 TMX 171 CP 170 BR 169 T12 168 T11 167 VSS2 164~166 VDX2
34
201 X 200 X 199 X 198 CSB(D4) 197 X 196 SDA(D6)
C=1.0uF
7
27 COM33
VG
CSB 5
SDA SCLK
RESB 2 1
VDD
Ver 1.0
51/54
2007/01/29
250 RESERVATIO N
......
1 COM59
249 RESERVATIO N
..........................................
244 COM60 243 COMS 242 XV0S 238~241 XV0I 236~237 XV0O 235 V0S 231~234 V0I 229~230 V0O 228 VGS 224~227 VGI 222~223 VGO 221 T8 220 T7 219 T6 218 T5 217 T0 216 T4 215 T3 214 T2 213 T1 212 VRS 208~211 VSS1 204~207 VSS2 203 OSC
202 SA0(D0)
XV0 9
V0 8
28 SEG0
.............................................
Vss 6
201 SA1(D1)
200 SDA_OUT(D2) 199 SDA_OUT(D3)
C=1.0uF
7
27 COM33
VG
198 X 197 X
195 SCLK(D7)
129 SEG101
130 COMS 131 COM0
.............................................
ST7576
163 COM26 156 COM25 ...... 157 COM32
SYSTEM SIDE
FPC SIDE
ITO SIDE
194 VDD1 193 X 192 RD 191 WR 190 X 189 RESB 185~188 VDD2 181~184 VDD1 180 VSS2 179 VMO 178 VMO 177 VMO 176 PS0 175 PS1 174 PS2 173 TMY 172 TMX 171 CP 170 BR 169 T12 168 T11 167 VSS2 164~166 VDX2
34
196 SDA_IN(D6)
SDA SCLK
RESB 2 1
VDD
Ver 1.0
52/54
2007/01/29
250 RESERVATIO N
......
ST7576
Reference to ITO Layout
XV0O XV0S XV0I V0O V0S VDD2 V0I VDD1
Ver 1.0
VSS2
VSS1
VGO
53/54
VGS
VGI
2007/01/29
ST7576
ST7576 Serial Specification Revision History Version Date Description
1 All layer change 0.6a 2006/05/10 2 Fig arrange 3 Add reference to ITO layout 4 Test pin size is reduced 0.6b 0.6c 0.6d 2006/05/24 P11 2006/06/01 To remove the capacitor between V0 and XV0 2006/06/19 Modify function set P1 : Voltage converter ; display supply voltage range
P16: VSS1, VSS2
0.7a
2006/08/14 P17: Mode0, Mode1=>T11,T12
P34 : limit Vop application range
P36-P47: take off TBD 0.7b 0.7c 2006/10/05 Remove external V0 Modify P37 DC characteristic
2006/12/15 Modify P3 Modify display supply voltage range at P1 Modify VDX2O pin description at P16 Modify TEN to X in instruction table at P30 Modify V0, XV0 limit value to 15V at P36 Modify Max value of internal of DC characteristic at P37
1.0
2007/01/25
Ver 1.0
54/54
2007/01/29

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